# Assign Statement In Verilog

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If it’s not true, the expression within the first “else” which is another “if” statement is executed. If it’s true, the output is set to 10 otherwise the expression within the next “else” statement is evaluated.

As you can see, there’s another “if” statement within the “else” branch of Line 11.

A two-bit signal, “sel”, is used to choose the desired input and assign it to “out1”.

The code for this example is as: 1 module Mux4_to_1( 2 input wire a, 3 input wire b, 4 input wire c, 5 input wire d, 6 input wire [1:0] sel, 7 output reg out1 8 ); 9 always @* 10 case (sel) 11 2'b00: 12 out1 = a; 13 2'b01: 14 out1 = b; 15 2'b10: 16 out1 = c; 17 default: 18 out1 = d; 19 endcase 20 endmodule When “sel”=00, the output is equal to “a”. Figure 2 shows an ISE simulation of the above code.

When there is only one expression within a branch, the “begin” and “end” keywords can be removed.

A more complex functionality can be described by using nested “if” statements.​When the procedural statements under several branches of a “case” statement are the same, we can merge them in a single branch and make the code more compact and readable.For example, consider the truth table of a 4-to-2 priority encoder.This article explains the use of Verilog “If” and “Case” statements to describe a combinational circuit.We’ll also take a look at the Verilog “Casex” and “Casez” statements and briefly discuss the potential pitfalls of using these two statements.In a previous article describing combinational circuits in Verilog, we discussed that the Verilog conditional operator can be used to check a condition when making an assignment with the “assign” keyword.Inside an “always” block, we can use the Verilog “if” statement to implement a similar functionality.The following example clarifies this point: When “addr” is 001 or 011, “out” should be 00. What branch will be selected by the “casex” statement? 1 match x11 so the default branch should be chosen and "out" should be 00.However, as mentioned above, the bit locations that contain z or x values will be masked no matter they are in the branch expression or in the expression within the parentheses after the “casex” statement.When describing a combinational circuit using an “always” block, we should list all of the inputs in the sensitivity list.Instead of listing all those inputs, we can simply use @* as used in Line 6 above.

## Comments Assign Statement In Verilog

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